Processor with a full instruction set decoder and a partial instruction set decoder

ABSTRACT

An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.14/554,709 filed on Nov. 26, 2014 (now issued U.S. Pat. No. 10,437,596),which is incorporated herein by reference.

BACKGROUND

Processors and other instruction execution machines apply varioustechniques to increase performance. Pipelining is one technique employedto increase the performance of processing systems such asmicroprocessors. Pipelining divides the execution of an instruction (oroperation) into a number of stages where each stage corresponds to onestep in the execution of the instruction. As each stage completesprocessing of a given instruction, and processing of the giveninstruction passes to a subsequent stage, the stage becomes available tocommence processing of the next instruction. Thus, pipelining increasesthe overall rate at which instructions can be executed by partitioningexecution into a plurality steps that allow a new instruction to beginexecution before execution of a previous instruction is complete. Aprocessor that includes a single instruction pipeline can executeinstructions at a rate approaching one instruction per cycle.

SUMMARY

An apparatus and method for increasing performance in a processor, orother instruction execution device, while minimizing energy consumptionare disclosed herein. In one embodiment, a processor includes a firstexecution pipeline and a second execution pipeline. The first executionpipeline includes a first decode unit and a first execution control unitcoupled to the first decode unit. The first execution control unit isconfigured to control execution of all instructions executable by theprocessor. The second execution pipeline includes a second decode unit,and a second execution control unit coupled to the second decode unit.The second execution control unit is configured to control execution ofonly a subset of the instructions executable via the first executioncontrol unit.

In another embodiment, a method includes fetching an instruction to beexecuted by a processor. Whether the instruction is executable by afirst execution control unit configured to execute only a subset of allinstructions executable by the processor is determined. The instructionis directed to a second execution control unit configured to execute allinstructions executable by the processor based on the first executioncontrol unit not being configured to execute the instruction.

In a further embodiment, an instruction execution device includes afirst execution pipeline and a second execution pipeline. The firstexecution pipeline includes a first execution control unit and a firstdecode unit. The first execution control unit is configured to controlexecution of all instructions executable by the device, and to apply alloperand addressing modes supported by the device to access operands. Thefirst decode unit is coupled to the first execution control unit, and isconfigured to decode all instructions executable by the device. Thesecond execution pipeline includes a second execution control unit and asecond decode unit. The second execution control unit is configured tocontrol execution of only a subset of the instructions executable viathe first execution control unit, and to apply only register andimmediate addressing modes to access operands. The second decode unit iscoupled to the second execution pipeline, and is configured to decodeonly the subset of the instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention,reference will now be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of a processor in accordance with variousembodiments;

FIGS. 2 and 3 show diagrams of instruction execution in pipelines of aprocessor in accordance with various embodiments;

FIGS. 4 and 5 show performance of conventional processors relative to amulti-pipeline processor in accordance with various embodiments; and

FIG. 6 shows a flow diagram for a method for executing instructions in amulti-pipeline device in accordance with various embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, companies may refer to a component by different names. Thisdocument does not intend to distinguish between components that differin name but not function. In the following discussion and in the claims,the terms “including” and “comprising” are used in an open-endedfashion, and thus should be interpreted to mean “including, but notlimited to . . . .” Also, the term “couple” or “couples” is intended tomean either an indirect or direct electrical connection. Thus, if afirst device couples to a second device, that connection may be througha direct electrical connection, or through an indirect electricalconnection via other devices and connections. The recitation “based on”is intended to mean “based at least in part on.” Therefore, if X isbased on Y, X may be based on Y and any number of additional factors.The term “subset,” as used herein, means a “proper subset” that includesfewer than all the elements of a set from which the subset is derived.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of theinvention. Although one or more of these embodiments may be preferred,the embodiments disclosed should not be interpreted, or otherwise used,as limiting the scope of the disclosure, including the claims. Inaddition, one skilled in the art will understand that the followingdescription has broad application, and the discussion of any embodimentis meant only to be exemplary of that embodiment, and not intended tointimate that the scope of the disclosure, including the claims, islimited to that embodiment.

Superscalar processors include multiple instruction pipelines operatingin parallel in order to provide execution of more than one instructionper cycle. In a superscalar processor, the fetch unit can provide morethan one instruction per cycle, multiple instruction decoders determinewhich instructions can be executed in parallel, and multiple executionpipelines operate in parallel using redundant execution units. However,a superscalar processor generally has a much higher gate count andenergy consumption than a single-scalar processor, and in real-worldapplications the performance increase provided by a superscalarprocessor may be much less than the full capacity of the executionpipelines. Consequently, the energy consumed per task by a superscalarprocessor can be significantly higher than the energy consumed by asingle-scalar processor executing the same tasks. Increased per taskenergy consumption is one reason that superscalar processors are rarelyapplied in embedded systems that are directed to low energy consumptionapplications, such as applications in which long battery life isimportant.

Embodiments of the present disclosure include multiple executionpipelines arranged to increase the rate of instruction executionrelative to single-scalar processors, and to reduce energy consumptionin comparison to conventional superscalar processors. While conventionalsuperscalar processors include multiple instruction decoders, eachcapable of decoding the full instruction set of the superscalarprocessor, embodiments disclosed herein include a single decoder capableof decoding the full instruction set, and one or more additionaldecoders capable of decoding only a small subset of the full instructionset. Similarly, embodiments of the present disclosure include a singleexecution pipeline capable of executing the full instruction set, andone or more additional execution pipelines capable of executing only thesmall subset of the full instruction set. The small subset ofinstructions executable by the additional execution pipeline(s) includesinstructions most frequently executed in practical applications.

FIG. 1 shows a block diagram of a processor 100 in accordance withvarious embodiments. The processor 100 includes a fetch unit 102, adispatcher 104, a full execution control unit 110, a subset executioncontrol unit 112, a register file 116, and execution units 118. Theprocessor 100 may include various other components and subsystems thathave been omitted from FIG. 1 in the interest of clarity. For example,embodiments of the processor 100 may include instruction and/or datacaches, memory, communication devices, interrupt controllers, timers,clock circuitry, direct memory access controllers, and various othercomponents and peripherals.

The fetch unit 102 retrieves instructions to be executed by theprocessor 110 from a storage device, such as a random access memory. Thefetch unit 102 may include program counters that specify the location ofinstructions being retrieved, pre-fetching logic that retrieves andstores instructions for later execution, etc.

The dispatcher 104 assigns each instruction provided by the fetch unit102 for execution to one of the multiple execution pipelines of theprocessor 100, where each execution pipeline includes a decode unit andan execution control unit. In the embodiment of FIG. 1, the processor100 includes two execution pipelines. Other embodiments of the processor100 may include more than two execution pipelines. The dispatcher 104includes full decode unit 106 and subset decode unit 108. The decodeunits 106, 108 examine the instructions received from the fetch unit104, and translate each instruction into controls suitable for operatingthe associated execution control units, processor registers, and othercomponents of the processor 100 to perform operations that effectuateexecution of the instructions.

The full decode unit 106 is capable of decoding all instructions (i.e.,the full and complete instruction set) executable by the processor 100.The subset decode unit 108 is capable of decoding only a small subset ofthe instructions executable by the processor 100 (i.e., a small subsetof the instructions decodable by the full decoder 106). For example, thesubset decode unit 108 may be capable of decoding only the mostfrequently executed instructions or a selected ones of the mostfrequently executed instruction. Some embodiments of the subset decodeunit 108 may be capable of decoding only instructions that applyrelatively simple operand addressing (e.g., instructions applying onlyregister or immediate addressing modes).

The dispatcher 104 includes dependency logic 120 that identifiesdependencies (e.g., data dependencies) between instructions beingexecuted, and causes the decode units 106, 108 to resolve dependenciesidentified by the dependency logic 120. For example, on identificationof a dependency by the dependency logic 120, the decode unit decodingthe instruction subject to the dependency may delay transfer of theinstruction to the execution control unit until the dependency has beenresolved.

Each decode unit 106, 108 passes decoded instructions to thecorresponding execution control unit. Full decode unit 106 passesinstructions to full execution control unit 110 for execution, andsubset decode unit 108 passes instructions to subset execution controlunit 112 for execution. The full execution control unit 110 is a capableof executing all instructions (i.e., the full and complete instructionset) executable by the processor 100. The subset execution control unit112 is capable of executing only a small subset of the instructionsexecutable by the processor 100 (i.e., a small subset of theinstructions decodable by the full decoder 106). For example, the subsetexecution control unit 112 may be capable of executing only selectedinstructions that are most frequently executed by the processor 100.Some embodiments of the subset execution control unit 112 may be capableof executing only instructions that apply relatively simple operandaddressing (e.g., instructions applying only register or immediateaddressing modes).

The full execution control unit 110 may include multiple executionstages 114 to provide a high instruction execution rate over the entireinstruction set. The subset execution control unit 112 may include fewerexecution stages 114 than the full execution control unit 110. Forexample, only a single execution stage 114 may be provided via thesubset execution control unit 112 to execute the small subset ofinstructions executable by the subset execution control unit 112.

In some embodiments of the processor 100, the full decode unit 106 andfull execution control unit 110 may decode and execute instructions of acomplex instruction set (i.e., CISC instructions) and instructions of areduced instruction set (i.e., RISC instructions) executable by theprocessor 100, and the subset decode unit 108 and subset executioncontrol unit 112 may decode and execute only the RISC instructions. Insome embodiments of the processor 100, the subset decode unit 108 andsubset execution control unit 112 may decode and execute only a subsetof the RISC instructions executable by the processor 100. For example,the subset decode unit 108 and subset execution control unit 112 maydecode and execute only RISC instructions that apply only the ALU 122and/or that manipulate only operands stored in the register file 116 orprovided in the instruction itself (i.e., apply only register orimmediate addressing modes).

The execution units 118 include various function units (shift unit,multiply unit, etc.) applied by the execution control units 110, 112 tomanipulate data and perform other operations needed for instructionexecution. The full execution control unit 110 may have access to andapply any and all of the function units provided by the execution units118. The subset execution control unit 112 may have access to and applyfewer function units of the execution units 118 than the full executioncontrol unit 110. For example, the subset execution control unit 112 mayaccess and apply only the arithmetic logic unit (ALU) 122 in someembodiments. Some embodiments of the execution units 118 may includemore than one instance of a function unit to facilitate parallelinstruction execution in the execution pipelines. For example, theexecution units 118 may include more than one ALU 122 to allow parallelaccess to ALU 122 functionality by the full execution control unit 110and the subset execution control unit 112.

The register file 116 includes registers that store operands for accessand manipulation by the dispatcher 104, the full execution control unit110, the subset execution control unit 112, and the execution units 118.The number and/or width of the registers included in the register file116 may be different in different embodiments of the processor 100.

In practice, the performance gained by inclusion of the subset decoder108 and the subset execution control unit 112 in the processor 100 canapproach that provided by conventional superscalar implementations, byproviding parallel execution of the most frequently encounteredinstructions, while substantially reducing energy consumption relativeto conventional superscalar implementations. The circuitry added to theprocessor 100 to implement the subset decoder 108 and the subsetexecution control unit 112 is relatively small in comparison to thecircuitry of the full decoder 106 and the full execution control unit110. As a result, the energy consumed by the subset decoder 108 and thesubset execution control unit 112 is relatively low in comparison tothat consumed by the full decoder 106 and the full execution controlunit 110.

FIGS. 2 and 3 show diagrams of instruction execution in the processor100. In FIG. 2, the fetch unit 102 provides, in fetch cycle 202,instructions to be decoded and executed. The full decode unit 106decodes a first instruction in decode cycle 204, and the subset decodeunit 108 decodes a second instruction in decode cycle 206, which is inparallel with decode cycle 204. Execution of the decoded instructionsproceeds in parallel with full execution control unit 110 executing thefirst instruction in execution cycle 208. The second instruction isexecuted in parallel by the subset execution control unit 112, whichexecutes the second instruction in execution cycle 210. Execution of thesecond instruction completes in a single cycle, while execution of thefirst instruction requires multiple cycles.

FIG. 3 shows a multi-instruction execution sequence in the processor100. In the execution sequence of FIG. 3, performance of the processor100 is very similar to that achievable by a conventional superscalararchitecture because the execution timing is constrained by datadependencies. Executing selected instructions via the limited decodingand execution capabilities of the subset decode unit 108 and the subsetexecution control unit 112 can reduce the energy consumed by executionof the instruction sequence with little or no reduction in performance.

Instructions 1 and 2 are executed in parallel as explained with regardto FIG. 2. Instructions 3 and 4 are fetched in cycle 2, but a dependency304 between the instructions causes the dispatcher 104 to delayexecution of instruction 4 for one cycle. Accordingly, instruction 4 isdecoded in cycle 4 in parallel with execution of instruction 3.Execution of instructions 3 and 4 may be performed in either of thepipelines of processor 100 that provide suitable decoding and executionfunctionality. In some embodiments, execution by the subset decode unit108 and subset execution control unit 112 may be selected to reduceenergy consumption.

Instructions 5 and 6 are fetched in cycle 3. Decoding of instruction 5is delayed until cycle 5 due to dependency 310. Instruction 5 is acomplex instruction that requires multiple execution cycles in the fullexecution control unit 110 to complete. Instruction 6 is also a complexinstruction that must be executed in the full execution pipeline.Therefore, decoding of instruction 6 is delayed until cycle 6. In theinstruction sequence of FIG. 3, instruction 6 is the only instructionfor which decoding and subsequent execution is delayed by the limiteddecoding and execution capabilities of the subset decode unit 108 andthe subset execution control unit 112 when compared to execution by aconventional superscalar implementation.

Instructions 7 and 8 are fetched in cycle 4 and execution is delayed.Instruction 7 is decoded by the subset decode unit in cycle 6, andexecuted in the subset execution control unit in cycle 7. Instruction 8is decoded by the subset decode unit 108 in cycle 7, and executed in thesubset execution control unit 112 in cycle 8. In various embodiments,instruction 8 may be executed in either pipeline of the processor 100.

FIGS. 4 and 5 show performance of conventional processors relative tothe processor 100. In FIG. 4, execution performance for a practicalapplication exhibiting low instruction parallelism (e.g. due to asubstantial number of instruction dependencies) is shown. Because of thelow instruction parallelism, performance of the processor 100 and theconventional superscalar processor are only slightly better than that ofthe single-scalar processor. The energy consumption of the processor 100is slightly higher than that of the single-scalar processor, and theenergy consumption of the conventional superscalar processor issubstantially higher that the single-scalar processor and the processor100.

FIG. 5 shows performance for a practical application exhibiting highinstruction parallelism. Performance of both the conventionalsuperscalar processor and the processor 100 is significantly higher thanthat of the single-scalar processor, with the conventional superscalarprocessor performing slightly better than the processor 100. However,the energy consumption of the conventional superscalar processor issubstantially higher than single-scalar processor, and the processor 100consumes less energy that the single-scalar processor. Thus, as shown inFIGS. 4 and 5, the processor 100 can provide a substantial performanceincrease over a single-scalar processor while consuming much less energythan a conventional superscalar processor.

FIG. 6 shows a flow diagram for a method 600 for executing instructionsin accordance with various embodiments. Though depicted sequentially asa matter of convenience, at least some of the actions shown can beperformed in a different order and/or performed in parallel.Additionally, some embodiments may perform only some of the actionsshown.

In block 602, the fetch unit 102 fetches instructions from memory forexecution and provides the fetched instructions to the dispatcher 104.

In block 604, the dispatcher 104 evaluates an instruction received fromthe fetch unit 102, and determines whether the instruction can beexecuted by the subset execution pipeline (e.g., the subset decoder 108and subset execution control unit 112). As explained above, the subsetexecution pipeline executes only a small subset of the full instructionset executable by the processor 100. For example, the subset executionpipeline may execute only RISC instructions or a subset of the RISCinstructions executable by the processor 100, while the full instructionpipeline can execute any and all instructions (including CISCinstructions) executable by the processor 100.

If, in block 606, the subset execution pipeline is deemed capable ofexecuting the instruction evaluated by the dispatcher 104, then in block608, the dispatcher 104 routes the instruction to the subset decoder108. The subset decoder 108 decodes the instruction.

In block 610, the subset decoder 108 passes the decoded instruction tothe subset execution control unit 112, and the subset execution controlunit 112 applies the execution units 118 to execute the instruction. Insome embodiments, the subset execution control unit 112 executes theinstruction in a single cycle.

If, in block 606, the subset execution pipeline is deemed incapable ofexecuting the instruction evaluated by the dispatcher 104, then in block612, the dispatcher 104 routes the instruction to the full decoder 106.The full decoder 106 decodes the instruction.

In block 614, the full decoder 106 passes the decoded instruction to thefull execution control unit 110, and the full execution control unit 110applies the execution units 118 to execute the instruction. In someembodiments, the full execution control unit 110 executes theinstruction in a multiple cycles.

While embodiments of the present disclosure have been described withreference to the processor 100, embodiments of the multi-pipelinearrangement disclosed herein may be applied to improve performance whileminimizing energy consumption in a wide variety of instruction executiondevices.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. A processing device comprising: a first executionpipeline including: a first decode unit configured to decode a firstinstruction, the first instruction being any instruction within a set ofinstructions the processing device is configured to execute; and a firstexecution control unit that includes a first number of execution stagesand is configured to execute the first instruction; a second executionpipeline separate from the first execution pipeline and including: asecond decode unit configured to decode a second instruction, the secondinstruction being any instruction within a subset of the set ofinstructions; and a second execution control unit that includes a secondnumber of execution stages and is configured to execute the secondinstruction, wherein the second number is less than the first number. 2.The processing device of claim 1, comprising: an instruction busconfigured to receive instructions including the first and secondinstructions; and an instruction fetch unit coupled to the instructionconfigured to receive the first and second instructions from theinstruction bus; wherein the first execution pipeline is configured toreceive the first instruction from the instruction fetch unit and thesecond execution pipeline is configured to receive the secondinstruction from the instruction fetch unit.
 3. The processing device ofclaim 1, comprising: a plurality of execution units; wherein the firstexecution control unit is configured to access any one of the executionunits to execute the first instruction; and wherein the second executioncontrol unit is configured to access only a subset of the executionunits to execute the second instruction.
 4. The processing device ofclaim 3, wherein the plurality of execution units comprises at least twoor more of an arithmetic logic unit (ALU), a shift unit, a multiplyunit, a floating point unit, or a load/store unit.
 5. The processingdevice of claim 4, wherein the second execution unit is configured toaccess only the ALU.
 6. The processing device of claim 1, wherein theset of instructions the processing device is configured to executeincludes instructions of a complex instruction set (CISC instructions)and instructions of a reduced instruction set (RISC instructions). 7.The processing device of claim 6, wherein the subset of the set ofinstructions are only the RISC instructions of the set of instructions.8. The processing device of claim 6, wherein the second executioncontrol unit is configured to execute only the RISC instructions of theset of instructions and not the CISC instructions of the set ofinstructions.
 9. The processing device of claim 1, wherein the firstexecution pipeline and the second execution pipeline are configured todecode the first instruction via the first decode unit and decode thesecond instruction by the second decode unit in the same processingcycle.
 10. The processing device of claim 1, wherein: the set ofinstructions includes all instructions of a reduced instruction set(RISC instruction set); the first instruction is any one of theinstructions of the RISC instruction set; and the second instruction isany one instruction of only a subset of the RISC instruction set. 11.The processing device of claim 1, wherein the second instruction is oneof a subset of the set of instructions that is identified asstatistically executed by the processing device at a higher frequencythan instructions of the set of instructions that are not part of thesubset.
 12. The processing device of claim 1, wherein the first numberis at least four, the first execution control unit includes at leastfour execution stages, and the second execution control unit includesless than four execution stages.
 13. The processing device of claim 1,wherein the second number is one, the second execution control unitincludes a single execution stage, and the first execution control unitincludes two or more execution stages.
 14. A system comprising: aprocessor that includes: an instruction bus; an instruction fetch unitconfigured to receive an instruction from the instruction bus; a fullset execution pipeline configured to execute any instruction of a set ofinstructions the processor is configured to execute; a subset executionpipeline separate from the full set execution pipeline and configured toexecute any instruction of only a subset of the instructions theprocessor is configured to execute; and a dispatch unit coupled to theinstruction fetch unit and configured to: determine whether the receivedinstruction is executable by the subset execution pipeline; supply thereceived instruction to the subset execution pipeline when the receivedinstruction is determined to be executable by the subset executionpipeline; and supply the received instruction to the full set executionpipeline when the received instruction is determined to not beexecutable by the subset execution pipeline.
 15. The system of claim 14,wherein determining whether the received instruction is executable bythe subset execution pipeline includes determining whether the receivedinstruction is part of the subset the instructions the processor isconfigured to execute.
 16. The system of claim 14, wherein the subsetexecution pipeline includes fewer execution stages than the full setexecution pipeline.
 17. The system of claim 16, wherein: the full setexecution pipeline includes a full decode unit; the subset executionpipeline includes a subset decode unit; in response to determining thatthe received instruction is executable by the subset execution pipeline,the received instruction is decoded by the subset decode unit and thenexecuted by the subset execution pipeline; and in response todetermining that the received instruction is not executable by thesubset execution pipeline, the received instruction is decoded by thefull decode unit and then executed by the full set execution pipeline.